Rendered at 07:56:01 GMT+0000 (Coordinated Universal Time) with Cloudflare Workers.
woodruffw 14 hours ago [-]
I’m a fan of this, although I’m concerned about the security/trust model: using a third-party CI orchestrator on top of GHA means trusting them with all of your secrets, potentially sensitive logs, etc. Those concerns are somewhat lessened in the context of public repos, but even public repos contain nontrivial workflows that use configured secrets.
stabbles 14 hours ago [-]
My experience with RISC-V so far is that the chips are not much faster than QEMU emulation. In other words, it's very slow.
LeFantome 13 hours ago [-]
That has been the case so far but is changing this year.
The SpacemiT K3 is faster than QEMU. Much faster chips are expected to release over the next few months.
I mean things like the Milk-V Pioneer were already faster but expensive.
One thing that has been frustrating about RISC-V is that many companies close to releasing decent chips have been bought and then those chips never appear (Ventana, Rivos, etc). That and US sanctions (eg. Sophgo SG2380).
mshockwave 8 hours ago [-]
One thing I observed is that RVV code is usually slower in QEMU
OsrsNeedsf2P 14 hours ago [-]
Oftentimes slow is fine, when the work is parallel and the hardware is cheap
LeFantome 8 hours ago [-]
RISC-V microcontrollers are inexpensive but “application” processors will be expensive until volumes increase.
Performance will get “good enough” over the next 2 years. Prices will drop after that.
detaro 8 hours ago [-]
That the "good enough" SoCs will be arriving "over the next 2 years" is what the RISC-V advocates have told us for quite a few years now.
pelasaco 12 hours ago [-]
which, sadly, isnt the case right now
dlcarrier 11 hours ago [-]
It is the case for embedded microcontrollers. An ESP32-C series is about as cheap as you can get a WiFi controller, and it includes one or more RISC-V cores that can run custom software. The Raspberry Pi Pico and Milk-V Duo are both a few dollars and include both ARM and RISC-V view. with all but the cheapest Duo able to run Linux.
wyldfire 9 hours ago [-]
Some of that could be related to the ISA but I'm hoping that it's just the fact that the current implementations aren't mature enough.
The vast majority of the ecosystem seems to be focused on uCs until very recently. So it'll take time for the applications processors to be competitive.
LeFantome 8 hours ago [-]
The RISC-V ISA can be fast.
Tenstorrent Ascalon, expected later this year, is expected to be AMD Ryzen 5 speeds. Tenstorrent hopes to achieve Apple Silicon speeds in a few years.
The SpacemiT K3 is about half as fast as Ascalon and available in April. K3 is 3-4 times faster than the K1 (previous generation).
This should give you an idea about how fast RISC-V is improving.
pjmlp 41 minutes ago [-]
Assuming AMD, Intel, ARM, Apple in a few years haven't released new CPUs, otherwise the difference is the same as today.
adgjlsfhk1 3 hours ago [-]
I'd be pretty surprised if Ascalon actually hits Zen 5 perf (I'm gessing more like Zen2/3 for most real world workloads). CPU design is really hard, and no one makes a perfect CPU in their first real generation with customers. Tenstorrent has a good team, but even the "simple" things like compilers won't be ready to give them peak performance for a few years.
snvzz 2 hours ago [-]
>I'd be pretty surprised if Ascalon actually hits Zen 5 perf
Certainly not in the Atlantis SoC, due to the older fab node used. Zen2-3 territory IPC is the expectation, with lower clocks than these actually got.
By the time they have the necessary scale to use the best fabs, they'll be tapping out something newer than the Ascalon that went into Atlantis.
Tenstorrent expects to reach parity with the best x86 and arm chips by 2028.
k_roy 10 hours ago [-]
Same experience here.
At least for SBCs, I’ve bought a few orange pi rv2s and r2s to use as builder nodes, and in some cases they are slower than the same thing running in qemu w/buildx or just qemu
snvzz 8 hours ago [-]
The arrival of the first RVA23 chips, which is expected next month, will change the status quo.
Besides RVA23 compliance, these are dramatically faster than earlier chips, enough for most people's everyday computing needs i.e. web browsing, video decoding and such. K3 got close to rpi5 per-core performance, but with more cores, better peripherals, and 32GB RAM possible, although unfortunately current RAM prices are no good.
And it'll only get better from there, as other, much faster, RVA23 chips like Tenstorrent Alastor ship later this year.
snvzz 2 hours ago [-]
s/Alastor/Atlantis/g.
Alastor is something else; a core from Tenstorrent that is considerably smaller than Ascalon.
peaklineops 6 hours ago [-]
The security concern raised here is worth thinking through. Third-party CI runners see your workflow environment — that's the actual trust boundary.
For public repos (the primary target here), the bigger practical concern is usually the opposite: your workflows fire webhooks to external systems and you have no visibility into what those systems actually received. This is especially true when integrating notification or deployment hooks that run after a successful test suite. The architecture step (source → RISC-V runner → build artifact → deployment hook) adds another hop where payloads can be malformed or swallowed silently.
The Linux Foundation backing does address the trust question well. RISE's membership list reads like a who's who of RISC-V commercial stakeholders — the incentive structure is to build trust in the ecosystem, not undermine it.
camel-cdr 14 hours ago [-]
Sadly still on quite old hardware, with no RVV.
Hopefully scaleway will have some newer servers in the future and this can be simply updated to the new devices.
Very good move. Hopefully GitHub won't ruin this with their CI charging changes.
singpolyma3 13 hours ago [-]
GitHub only :(
boredatoms 13 hours ago [-]
..is this RVA23?
LeFantome 13 hours ago [-]
Not yet
RV64GC (C910 cores)
Western0 14 hours ago [-]
Perfect for snooping on other people’s projects. No one in their right mind would touch this. It’s cheaper to buy the board yourself.
jubilanti 13 hours ago [-]
Yes, what a devious plan: give open source software projects a free CI service so you can... read their open source software code?
downrightmike 13 hours ago [-]
diabolical
throawayonthe 13 hours ago [-]
devious
sethops1 12 hours ago [-]
duplicitous
jrave 22 minutes ago [-]
dastardly
mhitza 14 hours ago [-]
It seems to be a Linux Foundation project, my trust is implicit higher than what you're claiming. Why wouldn't you trust them?
It's also aimed at open-source projects, for free, with the intent to improve RISC-V support.
heliumtera 7 hours ago [-]
Why would you trust anyone offering free candies?
PufPufPuf 1 hours ago [-]
Depends on the context. I'd trust the lady giving free candy samples in a candy store. The incentive is clear here, too: RISC-V needs adoption.
LeFantome 14 hours ago [-]
RISE is supported by many legit companies. Stealing is for sure not the intent.
The idea is to promote testing on RISC-V and to eliminate lack of hardware for being the reason not to. Obviously, low budget projects and Open Source are the primary targets. Commercial products can afford real RISC-V hardware.
The SpacemiT K3 is faster than QEMU. Much faster chips are expected to release over the next few months.
I mean things like the Milk-V Pioneer were already faster but expensive.
One thing that has been frustrating about RISC-V is that many companies close to releasing decent chips have been bought and then those chips never appear (Ventana, Rivos, etc). That and US sanctions (eg. Sophgo SG2380).
Performance will get “good enough” over the next 2 years. Prices will drop after that.
The vast majority of the ecosystem seems to be focused on uCs until very recently. So it'll take time for the applications processors to be competitive.
Tenstorrent Ascalon, expected later this year, is expected to be AMD Ryzen 5 speeds. Tenstorrent hopes to achieve Apple Silicon speeds in a few years.
The SpacemiT K3 is about half as fast as Ascalon and available in April. K3 is 3-4 times faster than the K1 (previous generation).
This should give you an idea about how fast RISC-V is improving.
Certainly not in the Atlantis SoC, due to the older fab node used. Zen2-3 territory IPC is the expectation, with lower clocks than these actually got.
By the time they have the necessary scale to use the best fabs, they'll be tapping out something newer than the Ascalon that went into Atlantis.
Tenstorrent expects to reach parity with the best x86 and arm chips by 2028.
At least for SBCs, I’ve bought a few orange pi rv2s and r2s to use as builder nodes, and in some cases they are slower than the same thing running in qemu w/buildx or just qemu
Besides RVA23 compliance, these are dramatically faster than earlier chips, enough for most people's everyday computing needs i.e. web browsing, video decoding and such. K3 got close to rpi5 per-core performance, but with more cores, better peripherals, and 32GB RAM possible, although unfortunately current RAM prices are no good.
And it'll only get better from there, as other, much faster, RVA23 chips like Tenstorrent Alastor ship later this year.
Alastor is something else; a core from Tenstorrent that is considerably smaller than Ascalon.
For public repos (the primary target here), the bigger practical concern is usually the opposite: your workflows fire webhooks to external systems and you have no visibility into what those systems actually received. This is especially true when integrating notification or deployment hooks that run after a successful test suite. The architecture step (source → RISC-V runner → build artifact → deployment hook) adds another hop where payloads can be malformed or swallowed silently.
The Linux Foundation backing does address the trust question well. RISE's membership list reads like a who's who of RISC-V commercial stakeholders — the incentive structure is to build trust in the ecosystem, not undermine it.
RV64GC (C910 cores)
It's also aimed at open-source projects, for free, with the intent to improve RISC-V support.
The idea is to promote testing on RISC-V and to eliminate lack of hardware for being the reason not to. Obviously, low budget projects and Open Source are the primary targets. Commercial products can afford real RISC-V hardware.
This is who you are trusting: https://riseproject.dev/members/